Plant 2 · PCBA hall B · floor plan rev C · sample data
Live state per station. Queue = items waiting in front of it (panels before depanel, boards after); cap is the physical buffer. Cycle s is editable.
| Zone | Station | Resources | Cycle s | Yield | State | Queue / cap | Util |
|---|
A deliberately small model of a real-shaped floor. Two inline SMT lines (one newer, one older) unload into a shared magazine rack. The back-end is a set of cells, not a line: odd-form insertion by cobots and an operator, selective solder, a depanel router that turns one panel into several boards, banks of parallel ICT and FCT testers, an off-line rework bench that feeds failed items back upstream, a manual box-build U-cell and packing. Operators carry cycle-time variability and take breaks; machines carry random stoppages. It answers one question well: where does WIP pile up when you change staffing, testers or panelisation. It is not a schedule and not a control system. Rebuilt in the room from a floor plan and a process sheet across the Day 2 afternoon: the flow graph and simulator first, the 3D last.